The invention relates to a technique for compensating the output produced by an input stage of a high speed integrated circuit operational amplifier, and more particularly to providing a pair of linear compensation capacitors to compensate relatively large and small collector-to-substrate capacitances of a PNP "folded cascode" transistor and an NPN cascode transistor, respectively, the collectors of which apply two output signals with a constant voltage difference between them to the bases of PNP and NPN input transistors of a diamond follower buffer circuit.
FIG. 2 shows a known prior art technique of applying a pair of output signals that have a constant voltage difference between them to the PNP and NPN input transistors, respectively, of a diamond follower buffer. This technique provides a constant voltage difference between conductors 34 and 35 connected to the base electrodes of diamond follower input transistors 51 and 52, respectively, and was developed to reduce the "standing current" or quiescent current through output transistors 56 and 57 without having to use excessively large physical sizes of the input transistors 51 and 52 (see FIG. 1B) of the diamond follower.
PNP transistor 18 is a "folded cascode" vertical transistor, the emitter of which is coupled to the output of an input stage which is not shown in FIG. 2, but is shown as stage 3 in FIG. 1A. The base of folded cascode transistor 18 is connected to the base of a PNP current mirror control transistor 15 as in FIG. 1A. The collector-to-substrate capacitance C.sub.CS(18) of PNP folded cascode transistor 18 is quite high, and in fact is approximately 20 times greater than the collector-substrate capacitance C.sub.CS(38) of NPN cascode transistor 38, due to the characteristics of the manufacturing process used to fabricate "vertical" PNP transistors in the integrated circuit.
A pair of low value resistors 32A and 32B are connected in series between the collector of PNP folded cascode transistor 18 and the collector of NPN cascode transistor 38. The bias current through the series-connected string of elements including PNP folded cascode transistor 18, resistors 32A and 32B, and NPN cascode transistor 38 establishes a constant voltage drop across the pair of resistors 32A and 32B and hence between conductors 34 and 35. Conductors 34 and 35 are connected to the base electrodes of NPN input transistor 52 and PNP input transistor 51, respectively, of a diamond follower 20. PNP junction capacitors 54 and 55 are connected as shown between conductors 34 and 35, respectively, to improve differential gain and phase of operational amplifier 30. In accordance with the closest prior art known to the applicant, only one linear compensation capacitor 46A is provided, as shown in prior art FIG. 2; it has a value of 0.5 picofarads and is connected between -V.sub.EE and the conductor 50 joining resistors 32A and 32B.
However, the prior art capacitive compensation technique shown in FIG. 2 does not provide the capacitive compensation needed to avoid the instability (i.e., oscillation) shown by character A in waveform 60 of FIG. 3. Such instability is, of course, completely unacceptable in a high frequency operational amplifier.